Job Description

Description

• The ideal candidate will be required to work on both IP development and integration into SoCs catering to various markets and tech nodes. The job will involve RTL design, front-end tools flow, and SoC integration/porting-related tasks.

Job Description

·       Interacting closely with the product definition and architecture team.

·       Developing implementation (micro architecture and coding) strategies to meet quality, and PPAS (Performance Power Area Schedule) goals for Sub-system.

·       Define various aspects of the block level design such as block diagram, interfaces, clocking, transaction flow, pipeline, low power etc.

·       Perform as well as lead a team of engineers on RTL coding for Sub-system/SOC integration, function/performance simulation debug.

·       Drive Lint/CDC/FV/UPF checks to ensure design quality.

·       Develop Assertions as part of white-box testing-coverage.

·       Knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE,SDCC and Avalon.

·       Understanding of Memory controller and microprocessors designs is an added advantage.

·       Hands on experience in Multi Clock designs, Asynchronous interface is a must.

·       Experience in Synthesis / Understanding of Constraint development and timing concepts is a plus.

·       Working with Power and Synthesis teams on use cases, dynamic power and data-path interactions.

·       Experience in using the tools in ASIC development such as Lint, Design compiler and Primetime is required.

·       Scripting: Proficient in Python, TCL.

General Requirements

·       Bachelor's degree or Master’s degree in Electronics or similar.

·       Excellent problem-solving and troubleshooting skills.

·       Strong written, verbal, and telephonic communication skills.

·       Excellent research and interpersonal skills.

·       Strong analytical skills.